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CMX018
UHF FM/FSK Receiver
D/018/3 April 1999 Advance Information
Features
* * * * * * *
Applications
* * * * * * *
Double Conversion Super-Heterodyne Receiver and FM/FSK Demodulator LNA with Switched Gain High Performance UHF Down-Converter Stage with Integrated VCO 2.7V Operation Zero-Power Mode (<10A) 28-Pin SSOP Package Temperature Compensated RSSI
High Performance Analogue/Digital Radio Links (860-965MHz) General ISM 915MHz Band Analogue/Digital Cordless Phones Spread Spectrum Receivers Analogue FM Receivers Handheld Data Terminals So-Ho Wireless Data Links
GAINSEL
TANK
OSCOUT
OSCBA
OSCEM
ENABLE
RSSI
BUFFERED OSCILLATOR OUTPUT
BANDGAP & BIAS CONTROL 2nd DOWN CONVERTER
1st DOWN CONVERTER
LNAIN 50 50
VCO
IF LIMITING AMPLIFIER FM/FSK DISCRIMINATOR
LNA
DETOUT
50
100
100
430
430
LNADEC
LNAOUT
MIX1IN
MIX1OUT
MIX2IN
MIX2OUT
LIMIN
LIMDEC1 LIMDEC2
LIMOUT
QUADIN
1.1
Brief Description
The CMX018 is a single chip UHF FM/FSK double-conversion super-heterodyne receiver. It combines a dual gain mode Low Noise Amplifier (LNA), two down-converters (including integrated oscillators), limiting amplifier, RSSI, FM/FSK demodulator and zero-power mode control. The CMX018 can be used in conjunction with the CMX017, an integrated FM/FSK modulator and transmitter, to implement a complete UHF radio link.
CONTENTS Section Page
1.0 Features and Applications ............................................................................ 1 1.1 Brief Description ............................................................................................ 1 1.2 Internal Block Diagram .................................................................................. 3 1.3 Signal List ....................................................................................................... 4 1.4 External Components .................................................................................... 6 1.5 General Description ....................................................................................... 7 1.5.1 Low Noise Amplifier....................................................................... 7 1.5.2 First Down-Converter .................................................................... 7 1.5.3 Second Down-Converter ............................................................... 7 1.5.4 Limiting Amplifier and RSSI.......................................................... 7 1.5.5 FM/FSK Demodulator..................................................................... 8 1.5.6 Zero-Power Mode ........................................................................... 8 1.6 Application Notes........................................................................................... 9 1.6.1 General ............................................................................................ 9 1.6.2 Example Schematic and Layout ................................................... 9 1.7 Performance Specification .......................................................................... 12 1.7.1 Electrical Performance ................................................................ 12 1.7.2 Packaging ..................................................................................... 15 1.7.3 Handling Precautions .................................................................. 15
Note:
As this product is still in development, it is likely that a number of changes and additions will be made to this specification. Items marked TBD or left blank will be included in later issues. Information in this data sheet should not be relied upon for final product design.
(c) 1999 Consumer Microcircuits Limited
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D/018/3
1.2
Internal Block Diagram
LNAIN
1 LNA
28
ENABLE
GND
2
27
GAINSEL
LNAOUT
3
26
LNADEC
GND
4 FIRST DOWN CONVERTER
25
Vcc1
MIX1IN
5
24
GND
MIX1OUT
6
23
TANK
GND
7 BUFFERED VCO OUTPUT
22
Vcc2
MIX2IN
8
21
OSCOUT
MIX2OUT
9 SECOND DOWN CONVERTER
20
OSCBA
GND 10
19
OSCEM
LIMIN 11
IF LIMITING AMPLIFIER
430
18
DETOUT
LIMDEC1 12
17 FM/FSK DEMODULATOR
Vcc3
LIMDEC2 13
16
LIMOUT
RSSI 14
15
QUADIN
Figure 1 Internal Block Diagram
(c) 1999 Consumer Microcircuits Limited
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D/018/3
1.3
Signal List
Package D6 Pin No. 1 2 3 4 5 6 7 8 9 10 Name
Signal
Description
Type I/P GROUND O/P GROUND I/P O/P GROUND I/P O/P GROUND LNA RF Input LNA Ground connection LNA RF Output LNA Ground connection RF Input to the First Down-Converter IF Output from the First Down-Converter First Down-Converter Ground connection RF Input to the Second Down-Converter IF Output from the Second Down-Converter Second Down-Converter, Limiting Amplifier, RSSI and Demodulator stages Ground connection Input to the Limiting Amplifier External Decoupling capacitors - one required at each Limiting Amplifier Input Receive Signal Strength Indicator output Quadrature input to the FM Demodulator Output from the Limiting Amplifier Power supply to the Second Down-Converter, Limiting Amplifier, RSSI and Demodulator stages - nominally 3.0V Output of the FM/FSK Quadrature Demodulator Emitter connection to the Second DownConverter Local Oscillator transistor Base connection to the Second Down-Converter Local Oscillator transistor O/P POWER Buffered Local Oscillator (Open-Collector) output from the First Down-Converter First Down-Converter Power supply - nominally 3.0V
LNAIN GND LNAOUT GND MIX1IN MIX1OUT GND MIX2IN MIX2OUT GND
11 12 13 14 15 16 17
LIMIN LIMDEC1 LIMDEC2 RSSI QUADIN LIMOUT Vcc3
I/P I/P I/P O/P I/P O/P POWER
18 19 20 21 22
DETOUT OSCEM OSCBA OSCOUT VCC2
O/P
(c) 1999 Consumer Microcircuits Limited
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D/018/3
Package D6 Pin No. 23 24 25 26 27 Name TANK GND VCC1
Signal
Description
Type I/P GROUND POWER First Down-Converter Local Oscillator (VCO) TANK/resonator connection First Down-Converter VCO Ground connection LNA Power supply - nominally 3.0V External LNA bias decoupling capacitor CMOS I/P LNA Gain control logic input. A logic '0' provides a typical power gain of 16dB and a logic '1' provides an attenuation of 6dB Zero-Power logic control. A logic '0' powers down the device.
LNADEC GAINSEL
28
ENABLE
CMOS I/P
Notes: I/P = O/P =
Input Output
(c) 1999 Consumer Microcircuits Limited
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D/018/3
1.4
External Components
Component Values: X1 L1 L2 L3 L4 D1 ~ C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 R1 R2 R3 60.175MHz 22nH 680nH 680nH 1H Varactor Resonator 100nF 100nF 100nF 200pF 8 - 50pF 5pF 220pF 6.8pF 15pF 33pF 4.7pF 6.2pF 10nF 100pF 100pF 10k 10k 2.0k 50ppm Xtal
Varactor Diode, type SMV1233-011 Co-Axial Resonator, type RG402, length = 11mm, shorted end.
Trimmer
NOTE: Components are surface mount, type SMD0603, unless otherwise marked.
Figure 2 Example of CMX018 with External Components
(c) 1999 Consumer Microcircuits Limited
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D/018/3
1.5
General Description
The CMX018 is a single chip UHF FM/FSK double-conversion super-heterodyne receiver. It combines a dual gain mode Low Noise Amplifier (LNA), two down-converters (including integrated oscillators), limiting amplifier, RSSI, FM/FSK demodulator and zero-power mode control. The receiver frequency is selected using an external PLL or synthesizer which is driven by the buffered RF oscillator signal from the first down-converter. The CMX018 can be used in conjunction with the CMX017, an integrated FM/FSK modulator and transmitter, to implement a complete UHF radio link.
1.5.1
Low Noise Amplifier The LNA includes a switched gain function which is used to increase the dynamic range of the receiver. The gain is selected using the GAINSEL logic input at pin 2. With a logic '0' at the GAINSEL input a high gain is selected and the amplifier achieves the lowest noise figure. This mode is used where maximum sensitivity is required for low level input signals. Where high level signals are present at the receiver input, which cause difficulties due to inter-modulation, the gain of the LNA can be reduced by typically 22dB from about +16dB to about -6dB. The attenuation is selected by applying a logic '1' at the GAINSEL input, this minimises the amount of non-linear distortion in the overall receiver at the expense of small signal sensitivity. The input and output impedances of the LNA are typically 50.
1.5.2
First Down-Converter The first down-converter includes a double balanced mixer with a low noise pre-amplifier and on-chip oscillator components. The oscillator is configured as a "high-sided" voltage controlled local oscillator, using an external varicap diode and tank resonator circuit, such that the first IF is typically centred at 70MHz. A buffered oscillator signal (OSCOUT at pin 21) is provided to drive the frequency synthesizer which controls the frequency tuning. The input impedance is typically 50 and the output impedance is typically 100.
1.5.3
Second Down-Converter The second down-converter also includes a double balanced mixer with a low noise pre-amplifier and on-chip oscillator components. The oscillator is configured as a "low-sided" local oscillator, using an external crystal at typically 60MHz, such that the second IF is centred at 10.7MHz. The input impedance is typically 100 and the output impedance is typically 430.
1.5.4
Limiting Amplifier and RSSI The limiting amplifier provides the IF amplification and limiting prior to the FM/FSK demodulator. An RSSI circuit is included which has temperature compensation. An RF signal level of -100dBm at the LNA input will produce an RSSI voltage of typically TBD mV. The RSSI voltage will increase with increasing RF input level at a rate of 20mV/dB up to a typical voltage of TBD V at a -60dBm RF input. In practice the absolute RSSI voltage will depend upon the insertion losses associated with each of the IF filters. The input impedance is typically 430.
(c) 1999 Consumer Microcircuits Limited
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D/018/3
1.5.5
FM/FSK Demodulator A quadrature detector is employed together with an external discriminator and phase shift network to demodulate the FM or FSK signal.
1.5.6
Zero-Power Mode The device is powered down by applying a logic '0' level at the ENABLE input (pin 28). In this mode the device current is reduced to less than 10A. This feature is useful when the device is operating within a transceiver where the receiver needs to be enabled and disabled. A delay should be allowed for the receiver to settle after power-up. This is likely to be less than the xtal oscillator stabilisation time, which may be altered by adjusting the value of R2, shown in Figure 2.
(c) 1999 Consumer Microcircuits Limited
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D/018/3
1.6
1.6.1
Application Notes
General TBD
1.6.2
Example Schematic and Layout The following schematic (Figure 3) and printed circuit layout (Figure 4) show a typical application interface for the CMX018. To aid legibility, the schematic and layout are available electronically from the CML website http://www.cmlmicro.co.uk or on floppy disk by request from CML's office. Alternative components and component values are shown on the schematic. These should be selected according to the intended application. The schematic uses the following ICs: U2 U3 U4 Motorola MC34072D-SO8 IC Works WB1315X Analog Devices AD8532-SO8
(c) 1999 Consumer Microcircuits Limited
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D/018/3
J2 RFIN C2 33pF C9 N/C C8 C24 100pF
1
C4 N/C C12 N/C C17
F5CH-915M-L2 2 5 IN OUT
C93 N/C FLT1
3V
C320
GND
C21
1346
GND GND GND GND
SAW FILTER
100pF L14 L15 1uF 100nF C36 1nF 10k-N/C 1nF C43 C45 4.7pF 1nF L7 680nH 33pF C57 15pF C63 C62 220pF C73 L8 680nH R18 N/C 10k-N/C C64 6.8pF
HC49U-S XT1
IN RXRESNR2
100pF L16 1nF 100nF R14 C37 100nF C33
GND GND GND GND
(c) 1999 Consumer Microcircuits Limited
N/C FLT2 C27
1 LNAIN ENABLE 28 GAINSEL 27 LNADEC 26
N/C N/C C34
3 LNAOUT
F5CH-915M-L2 5 OUT IN 2 SAW FILTER
C28 C35 100pF
4 GND2 2 GND1
100pF
5 MIX1IN OSCGND 24 TANK 23 VCC2 22 OSCOUT OSCBA 20 OSCEM 19 DETOUT VCC3 17 LIMOUT 16 QUADIN 15 18 21
100pF U4
VCC1 25 6 MIX1OUT 7 GND3
6431
C44 10pF D1 C46 3pF
C31 N/C
8
100pF C26 C55
9 MIX2OUT 10 GND4 11 LIMIN MIX2IN
C30 N/C C56 C41 C60
1 IN OUT GND 13 LIMDEC2 3
C38 CMX018D6
R15 10k C47
R16 100R 10nF
C39 1nF C69 10nF C68 100nF 5pF L10 C77 1uH 100nF 2k 200pF CV1206 R22 C72
12 LIMDEC1
C40 33pF L4 1nF C65 C66 100nF
RSSI 3 GND 14
360pF C42 L6 12.5nH U5
2
360pF 12.5nH C50
KMFC545S
1 IN OUT
33pF L5 8nH C52 C54
N/C R1 L9 L1 0R-N/C C1
C70 U6
2
180pF C49 120+33pF 120+47pF 120+33pF
KMFC545P
330pF C51
180pF C53
5V
1nF C5
Figure 3 Application Schematic
10
R10
1nF C6
C71
5V
15uH R3
1nF C3 N/C U1
8
2.2uF
R5
6p8 R4
100k
100k
2.2uF AD8532-SO8 C16
2
-
4
U2 N/C C14 C13 2k2 100pF J1 C61
2 4 6 8 1 1 3
C7 R47 C48 C59 C58 100pF 100pF 100pF L2 15uH
5V
C15
R2
6
1
-
7
3V
100nF 100pF 2.2uF C29 100pF L3 22nH R7 47K - N/C
3 2
+ 5 4 6
1
3
+
47nF
10k
5
8
+
MC34072D
( 7-NC)
C11
C32
R9
R6
VCC2 20
1nF C67 100pF 100pF C460 C470 100pF C25 C22 C81 1uF 1nF 100pF 100nF 3V C87 L11 820nH TFMCON20M C78 100uF 100nF 10nF C79 C80 100pF
2 3 4 5 6 7 8 9 10 VP1 DO1 GND FIN1
2.2uF
100k
0R C18
VP2 DO2 GND FIN2 19 18 17
VCC1
R8 470nF U3 WB1315X
FIN1B GND OSC_IN GND FO_LD 16 FIN2B GND LE DATA CLOCK 15 14 13 12 11
R100
5 7 9 10 12 14 16 18 20
100 C10
11
C19 C23 100pF C20 100pF 100nF
1k
100pF
15 17 19
13
5V SYNT_CLK SYNT_DATA SYNT_STB
R19 100k
R20 100k
R21 100k
D/018/3
Figure 4a Application Layout - Top Copper
Figure 4b Application Layout - Bottom Copper (not reversed)
Available from http://www.cmlmicro.co.uk
(c) 1999 Consumer Microcircuits Limited
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D/018/3
1.7
1.7.1
Performance Specification
Electrical Performance
Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device.
Supply Voltage (VCC) Input Voltage LNA Input Power
Pins 17, 22, 25 27, 28 1
Min. -0.3 -0.3
Max. 7.0 VCC + 0.3 0
Units V V dBm
D6 Package Total Allowable Power Dissipation at Tamb = 25C ... Derating Storage Temperature
Min.
-55
Max. 1100 11 +125
Units mW mW/C C
Operating Limits Correct operation of the device outside these limits is not implied. Notes Supply Voltage (VCC) RF Input Range Operating Temperature Min. 2.7 860 -10 Max. 3.3 965 +60 Units V MHz C
(c) 1999 Consumer Microcircuits Limited
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D/018/3
Operating Characteristics For the following conditions unless otherwise specified: VCC = 2.7V to 3.3V, Tamb = - 10C to +60C, RF = 915MHz, 50 source and load impedance. Pin DC Parameters Icc (ENABLE = VCC and GAINSEL = 0V) Icc (ENABLE = VCC and GAINSEL = VCC) Icc (ENABLE = 0V) AC Parameters LNA (RF = 915MHz) Power Gain (GAINSEL = 0V) Power Gain (GAINSEL = VCC) Noise Figure Input 1dB Gain Compression Point
(GAINSEL = 0V)
Min.
Typ. 50 42
Max.
Units mA mA A
17, 22, 25 17, 22, 25 17, 22, 25
10
1, 3 1, 3 1, 3 1 1 1 1 3, 1 3, 1 1 3 1 3 1
16 -6.0 3.0 -20 16 -10 25 -35 -6.0 50 50 10 15 -45
dB dB dB dBm dBm dBm dBm dB dB dB dB dBm
Input 1dB Gain Compression Point
(GAINSEL = VCC)
Input Third Order Intercept Point
(GAINSEL = 0V)
Input Third Order Intercept Point
(GAINSEL = VCC)
Reverse Isolation (GAINSEL = 0V) Reverse Isolation (GAINSEL = VCC) Input Impedance Output Impedance Input Return Loss (50 source) Output Return Loss (50 load) VCO to LNA Leakage First Down Converter (RF = 915MHz and IF = 70MHz) Conversion Gain Noise Figure Input 1dB Gain Compression Point Input Third Order Intercept Point Input Impedance Output Impedance Input Return Loss (50 source) Output Return Loss (50 load) Buffered oscillator output power RF to IF Leakage LO to IF Leakage LO to RF Leakage
5, 6 5, 6 5 5 5 6 5 6 21 5, 6 6 5
15 15 -12 -4.0 50 100 TBD TBD -10 TBD TBD TBD
dB dB dBm dBm dB dB dBm dB dBm dBm
(c) 1999 Consumer Microcircuits Limited
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D/018/3
Operating Characteristics (Continued) Pin Second Down Converter (RF = 70MHz and IF = 10.7MHz) Conversion Gain Noise Figure Output 1dB Gain Compression Point Output Third Order Intercept Point Input Impedance Output Impedance Limiting Amplifier and RSSI (IF = 10.7MHz) Bandwidth Internal Voltage Gain Input Impedance RSSI Dynamic Range RSSI Slope 1 RSSI Voltage Range Demodulator (IF = 10.7MHz) 2 Output Swing Output Impedance Min. Typ. Max. Units
8, 9 8, 9 9 9 8 9
24 13 -11 -2 100 430
dB dB dBm dBm
11, 16 11 11 14 14 14
40 74 430 TBD TBD TBD
MHz dBV dB V/dB V
18 18
TBD 1
mVp-p k
Notes:
1. Input power = TBD to TBD 2. 125kHz Deviation, 1k Load
(c) 1999 Consumer Microcircuits Limited
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D/018/3
UHF FM/FSK Receiver
CMX018
1.7.2
Packaging
Figure 5 28-Pin Plastic SSOP Mechanical Outline: Order as part no. CMX018D6
1.7.3
Handling Precautions This device is a high performance RF integrated circuit and is ESD sensitive. Adequate precautions must be taken during handling and assembly of this device.
CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. Specific testing of all circuit parameters is not necessarily performed.
1 WHEATON ROAD WITHAM - ESSEX CM8 3TD - ENGLAND
Telephone: +44 1376 513833 Telefax: +44 1376 518247 e-mail: sales@cmlmicro.co.uk http://www.cmlmicro.co.uk

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